The present invention relates to a field-effect transistor of a silicon-on-insulator (SOI) structure, and a method of manufacture thereof.
A SOI-structure MOS field-effect transistor can be driven at a lower power consumption and a higher speed than an ordinary MOS field-effect transistor.
A schematic view of an example of a SOI-structure MOS field-effect transistor is shown in FIG. 50. A buried oxide film 1100 formed by a silicon oxide layer is formed on a silicon substrate 1000. A source region 1200 and a drain region 1300 are provided in mutually separate locations on the buried oxide film 1100. A body region 1400 is formed on the buried oxide film 1100, between the source region 1200 and the drain region 1300. A gate electrode 1500 is formed on the body region 1400 with a gate insulation film therebetween.
The body region 1400 of the MOS field-effect transistor of FIG. 50 is in a floating state. Thus carriers generated by impact ionization tend to accumulate in the body region 1400. When carriers accumulate, the potential of the body region 1400 changes. This phenomenon is called the substrate floating effect. This causes various problems in the MOS field-effect transistor, such as the kink phenomenon and the parasitic bipolar effect.
A SOI-structure MOS field-effect transistor can suppress this substrate floating effect. A schematic view of such a MOS field-effect transistor is shown in FIG. 51. This MOS field-effect transistor is called a dynamic threshold-voltage MOSFET (DTMOS). It differs from the MOS field-effect transistor shown in FIG. 50 in that the body region 1400 and the gate electrode 1500 are placed in electrical contact. This connection makes it possible for excess carriers that have accumulated within the body region 1400 to be drawn out of the body region 1400. This stabilizes the potential of the body region, making it possible to prevent the occurrence of the substrate floating effect.
However, a DTMOS has another problem in that it can only be used in practice under low gate voltage conditions of a gate voltage on the order of 1 V or less. In other words, a voltage that is applied to the body region in a DTMOS is of the same magnitude as the voltage applied to the gate electrode thereof. The application of a voltage to the body region causes a forward bias voltage to be applied to the PN junction formed by the body region and the source region. Since the withstand voltage in the forward direction of a PN junction is usually on the order of 0.7 V, any increase in the gate voltage beyond that point will cause a large current to flow between the body region and the source region. This current will make it impossible to achieve the lower power consumption that is the objective of a SOI structure. Such a current would cause errors in the operation of the circuitry comprising the SOI structure. In addition, since a small forward-direction current flows between the body region and the source region, even when the DTMOS is used at a gate voltage of less than 0.7 V, this impedes any reduction in the power consumption.
An objective of the present invention is to provide a SOI-structure field-effect transistor and a method of manufacture thereof that make it possible to achieve a lower power consumption, even during use under conditions of a comparatively high gate voltage.
(1) One aspect of the present invention relates to a MOS field-effect transistor formed on a SOI substrate, the SOI-structure field-effect transistor comprising a source region, a drain region, a body region, a gate electrode, a gate insulation film, a first contact portion, a second contact portion, and a resistance portion. The body region is interposed between the source region and the drain region and includes a first end portion and a second end portion. The gate electrode is formed on the body region, with the gate insulation film interposing therebetween, and extends in a direction from the first end portion toward the second end portion. The first contact portion is formed on the first end portion side. The a gate signal interconnecting for transferring a gate signal that is to be input to the gate electrode is connected electrically to the gate electrode within the first contact portion. The second contact portion is formed on the second end portion side. The gate electrode is connected electrically to the body region in the second contact portion. The resistance portion is formed on the first end portion side. The gate electrode is connected electrically to the first contact portion through the resistance portion.
In a DTMOS, the body region and the gate electrode are placed in electrical contact. The body region and the source region form a PN junction. For that reason, when a positive voltage is applied to the gate electrode of an nMOS transistor, by way of example, this causes a forward-direction voltage to be applied to this PN junction. When a voltage that is greater than the forward-direction withstand voltage of this PN junction is applied between the gate electrode and the source region, this will cause a current to flow between the gate electrode and the source region. When the gate voltage increases, this current will also increase. Thus the power consumption of the DTMOS will increase when it is used under conditions of a comparatively high gate voltage.
In the SOI-structure MOS field-effect transistor in accordance with this aspect of the present invention, the gate electrode and the first contact portion are placed into electrical contact by the resistance portion. The forward-direction current that flows through the PN junction as described above is therefore restricted by this resistance portion, making it possible to reduce the current between the body region and the source region. As a result, the power consumption of the DTMOS may be reduced, even when the DTMOS is being used under conditions of a comparatively high gate voltage.
In addition, the first contact portion of the SOI-structure MOS field-effect transistor in accordance with the present invention, the first contact portion thereof is formed on a first end portion side and the second contact portion thereof is formed on a second end portion side. This aspect of the present invention makes it possible for the gate electrode itself to function as a resistor, because a current flows through the gate electrode.
Note that the SOI-structure MOS field-effect transistor in accordance with this aspect of the present invention may have the effect of reducing the power consumption, regardless of whether the field-effect transistor is partially depleted or fully depleted. This will be discussed in the Experimental Examples part of the Description of Preferred Embodiments.
A method of manufacturing a SOI-structure MOS field-effect transistor in accordance with another aspect of the present invention comprises following steps:
(a) forming a body region having a first end portion and a second end portion, on the SOI substrate;
(b) forming a gate electrode on the body region, extending from the first end portion towards the second end portion;
(c) using the gate electrode as a mask for implanting ions into the SOI substrate, to form a source region and a drain region, in such a manner that the body region is interposed therebetween;
(d) forming a first contact portion on the first end portion side, through which the gate electrode is electrically connected to a gate signal interconnecting for transferring gate signals to be input to the gate electrode, and a second contact portion on the second end portion side, through which the gate electrode is electrically connected to the body region; and
(e) forming a resistance portion on the first end portion side, for providing electrical contact between the gate electrode and the first contact portion, in the steps (b) to (d).
(2) The SOI-structure MOS field-effect transistor may be provided with an interconnecting portion described below. The resistance portion may be comprised within an interconnecting portion. The interconnecting portion may be formed on the first end portion side, and may electrically connect the gate electrode and the first contact portion. A part of the interconnecting portion may be utilized as the resistance portion, by making the width of the part of the interconnecting portion smaller than the width of a remaining part of the interconnecting portion.
The SOI-structure MOS field-effect transistor may control the resistance of the resistance portion by a suitable combination of the width of the part of the interconnecting portion and the length of the part of the interconnecting portion. In other words, when the width W is made large, the resistance will be small; when the width W is made small, the resistance will be large. When the length L is made large, the resistance will be large; when the length L is made small, the resistance will be small.
The SOI-structure MOS field-effect transistor may be manufactured by the following step:
Step (e) may further comprise a step of forming an interconnecting portion for providing electrical contact between the gate electrode and the first contact portion. The step of forming the interconnecting portion may be patterning of the interconnecting portion such as to reduce the width of a part of the interconnecting portion to smaller than the width of a remaining part of the interconnecting portion.
(3) The SOI-structure MOS field-effect transistor may be provided with an interconnecting portion described below. The resistance portion may be comprised within an interconnecting portion. The interconnecting portion may comprise a polysilicon film. The interconnecting portion may be formed on the first end portion side, and may electrically connect the gate electrode and the first contact portion. A part of the interconnecting portion may be utilized as the resistance portion, by making the impurity concentration of the part of the interconnecting layer lower than the impurity concentration of a remaining part of the interconnecting layer.
In the SOI-structure MOS field-effect transistor, the film that will become the interconnecting portion and the film that will become the resistance portion may be formed simultaneously, without increasing the area of the resistance portion.
The SOI-structure MOS field-effect transistor may be manufactured by the following step:
The step (e) may further comprise a step of forming an interconnecting portion including a polysilicon layer, and for providing electrical contact between the gate electrode and the first contact portion. The step of forming the interconnecting portion may be such as to make the impurity concentration of a part of the interconnecting layer lower than the impurity concentration of a remaining part of the interconnecting layer. One method of making the impurity concentration of the part of the interconnecting layer lower than the impurity concentration of the remaining part of the interconnecting layer may be to form a polysilicon film and then cover the part of that film with a mask. Ions may be implanted into that film. Since ions are not implanted into the part of the film, the impurity concentration of that the part of the film may be lower than the impurity concentration of the remaining part of the film.
(4) The SOI-structure MOS field-effect transistor may be provided with an interconnecting portion described below. The resistance portion may be comprised within an interconnecting portion. The interconnecting portion may be formed on the first end portion side, and may electrically connect the gate electrode and the first contact portion. A part of the interconnecting portion may be utilized as the resistance portion, by forming the part of the interconnecting portion from a polysilicon film alone and forming a remaining part of the interconnecting portion from a polysilicon film and a silicide film.
In the SOI-structure MOS field-effect transistor, the film that will become the interconnecting portion and the film that will become the resistance portion may be formed simultaneously, while reducing the resistance of the interconnecting portion.
The SOI-structure MOS field-effect transistor may be manufactured by the following step:
Step (e) may further comprise a step of forming an interconnecting portion for providing electrical contact between the gate electrode and the first contact portion. The step of forming the interconnecting portion may be such that a part of the interconnecting portion is formed of a polysilicon film alone and a remaining part of the interconnecting portion is formed of a polysilicon film and a silicide film. Such a configuration can make it possible to form the interconnecting portion by a method in which the silicide film is removed from the part of the interconnecting portion, or a method in which the silicide film is not formed over the part of the interconnecting layer, by way of example. The method of removing the silicide film from the part of the interconnecting portion may be as described below. The polysilicon film is first formed, then a refractory metal film is formed on the polysilicon film. The refractory metal film is annealed to form a silicide film. The silicide film on the part of the interconnecting portion is removed.
The method of ensuring that the silicide film is not formed on the part of the interconnecting portion is as described below. A polysilicon film is formed. A refractory metal film is then formed on the polysilicon film, at regions other than the region that forms a part of the interconnecting portion. The refractory metal film is annealed to form a silicide film.
(5) The SOI-structure MOS field-effect transistor may be provided with an interconnecting portion described below. The resistance portion may be comprised within an interconnecting portion. The interconnecting portion may be formed on the first end portion side, and may electrically connect the gate electrode and the first contact portion. A part of the interconnecting portion is utilized as the resistance portion by forming, the length of the interconnecting portion may be longer than a shortest distance between the first contact portion and the gate electrode.
This configuration lengthens the interconnecting portion by making the length of the interconnecting portion longer than the shortest distance between the first contact portion and the gate electrode. The entire interconnecting portion is utilized as the resistance portion. This distance could be at least 1 xcexcm, by way of example.
A configuration for ensuring that the length of the interconnecting portion is longer than the shortest distance between the first contact portion and the gate electrode could be as described below, by way of example. An element isolation layer may be disposed in a manner to surround the source region and the drain region. The interconnecting portion may take a circuitous path on a surface of the element isolation layer and is connected electrically to the first contact portion. In this configuration the resistance portion is formed on the element isolation layer, making it possible to efficiently utilize the region on the element isolation layer.
This configuration may be manufactured by the step described below. Step (e) may further comprise a step of forming an interconnecting portion for providing electrical contact between the gate electrode and the first contact portion. The step of forming the interconnecting portion may be patterning of the interconnecting portion such that the interconnecting portion takes a circuitous path and may be connected electrically to the first contact portion, on a surface of an element isolation layer that is disposed in a manner to surround the source region and the drain region.
(6) In the SOI-structure MOS field-effect transistor, the resistance of the resistance portion may be greater than the on-resistance of the field-effect transistor.
The resistance of the resistance portion may be at least ten times the on-resistance of the field-effect transistor. The magnitude of current flowing within the field-effect transistor is the magnitude of the current between the gate electrode and the source region (Igs) added to the magnitude of the current between the drain region and the source region (Ids). When the resistance of the resistance portion is made to be at least ten times the on-resistance of the field-effect transistor, the effects described below may be achieved. In other words, the magnitude of the current between the gate electrode and the source region may be reduced to less than one-tenth, in comparison with the magnitude of the current between the drain region and the source region. Variations on the order of 10% are inevitable in the electrical characteristics of semiconductor device. Thus, even if the magnitude of the current between the gate electrode and the source region is added to the magnitude of the current between the drain region and the source region, the total magnitude will still be within the margin of error for the magnitude of the drain-source current (Ids).